The present invention relates to a voltage controlled oscillators (VCOs) generally and, more particularly, to a method and/or architecture for a supply variation tolerant VCO.
Conventional voltage controlled oscillator (VCO) approaches are prone to output frequency jitter issues due to supply voltage (VDD) noise (i.e., variation). As supply voltages and the corresponding headroom decrease, the conventional approach of implementing regulators to reject VDD noise and reduce output frequency jitter is not practical.
It would be desirable to have a VCO that has an output frequency that is independent of VDD variation.
The present invention concerns an apparatus comprising a plurality of serially coupled delay cells configured to generate an output signal having a frequency varied in response to a control signal. Each of the delay cells may be configured to generate one or more intermediate signals in response to the control signal and present the intermediate signals to a next of the delay cells. One or more next to the last of the intermediate signals may be fed back to a first of the delay cells. One or more last of the intermediate signals may be presented as the output signal.
The objects, features and advantages of the present invention include providing a method and/or architecture for implementing a supply variation tolerant voltage controlled oscillator (VCO) that may (i) minimize and/or eliminate output frequency jitter due to supply voltage variations, (ii) provide a constant amount of current to change the output level at each delay change, (iii) have a delay change control current that is substantially independent of supply voltage, and/or (iv) have a reduced amount of output frequency jitter when compared to conventional VCO approaches.